2019 CICC Panels

Key issues and controversial topics are debated by leaders from the IC industry. CICC panel discussions are well known for their lively and thought-provoking discussions. The Q&A sessions provide the audience the opportunity to weigh in on the important issues.

Panel Sessions

Monday, April 15


Session 11 – Panel-Can Intelligent Automation Improve Custom/Analog Design

Monday, April 15, 4:20 pm, Room 408

Session Chair: Brian Mulvaney, NXP

Session Co-Chair: Farhana Sheikh, Intel Circuit Research Lab

For several decades the basic design flow for analog/custom integrated circuits has not changed: schematic capture, circuit simulation, and semi-manual layout. Will this still be true twenty years from now? Is the reason for lack of progress in better design automation because the problem is ‘too hard’? Or are analog designers unwilling to give up the art of design? Hardware resources for more and more simulation have never been better, but there seems to be an insatiable appetite to consume all available machines.  Can a more intelligent use of resources, perhaps using rapidly developing machine learning techniques, break this bottleneck?


Elad Alon, Univ. of California, Berkeley

Peng Li, Texas A&M University

John Khoury, Si Lab

Huang-Jin Li, Intel

Jeff Dyck, Siemens/Mentor

Tuesday, April 16

 Session 16 – Panel-Choices, and Consequences for Neural Network HW and Systems

Tuesday, April 16, 10:40 am, Salon D

Session Chair: Geoffrey Burr, IBM Research — Almaden

Session Co-Chair: Chia-Yu Chen

Modern neural networks and machine learning have been generating impressive real-world results, thanks to vast quantities of training data and the massive parallelism of GPUs.  There are now many design efforts seeking to implement custom hardware and systems for neural networks.  Such design efforts inherently involve critical choices, each with their own consequences.  Should one focus on forward-inference opportunities or training opportunities?  Opportunities in the cloud or at the edge?   Reducing the computational load by pruning and reduced precision makes enormous sense, but at what point do these choices affect the accuracy, the applicability of the hardware across many different workloads, and sufficient flexibility for future algorithmic developments?  Similarly, the choice of batch-size forces tradeoffs between efficiency and performance. Other topics worth discussing might be how to support flexible algorithm-hardware co-design despite the long lead time of hardware, the potential role of neuromorphic non-Von-Neumann architectures, and the potential role of “spiking” neurons. In this panel, we assemble a diverse group of academic and industry professionals to share their views on these choices and consequences


Naresh Shanbhag, University of Illinois, Urbana-Champaign

Jae-sun Seo, Arizona State University

Alicia Klinefelter, NVIDIA

David Fick, Mythic-AI

Naveen Verma, Princeton University


Session 20 – Panel-Research Direction Mismatches Between Industry and Academia

Tuesday, April 16, 4:00 pm, Room 408

Session Chair: David Yeh,

Session Co-Chair: Timothy Dickson, IBM T.J. Watson

For years, university CMOS IC design research has painted a vision and demonstrated concepts that were often deemed too risky for industry to tackle.  As a result, today’s industry benefits from university research in topics such as CMOS RF circuits, switched capacitor filters, and oversampled data converters, just to name a few.  However, a view of today’s research landscape seems to point towards a mismatch between academic research and the current IC industry.  Is university research paving a sufficiently long-term roadmap, or is industry too short-term focused to notice?  Can industry buy into university ideas that are proven in 65nm CMOS, but not in 14nm FinFET?  What does industry value more – student talent development, or technology demonstrations with record-breaking FoM?  And dare we even broach the subject of a ‘funding mismatch’?  Our panel of experts will dive into these topics – and many more!


Ram Krishnamurthy, Intel

Jim Wieser, Texas Instruments

Woogeun Rhee, Tsinghua University

Pavan Hanumolu, University of Illinois, Urbana-Champaign

Shiva Gowni, NXP