Keynote I: April 26, 2021 8:50am – 9:40am CDT
Title: “Technology and Architecture for The Next Decade of Compute”
Sam Naffziger, Senior Vice President, Corporate Fellow, and Product Technology Architect,
Advanced Micro Devices, Inc
Abstract: We are in a tumultuous phase in the computer industry as silicon node costs increase and performance benefits decrease while worldwide demand for high performance and AI processing explodes. Meeting that demand in an economically viable way demands more innovation from our industry than ever before, and on new dimensions of circuit design and architecture. In this talk, we will explore the challenges to meeting demand, the promising proof points from chiplet and accelerator designs while looking at the future opportunities including the implications to silicon, software and packaging technology and required dimensions of innovation.
Speaker’s Bio: Samuel Naffziger is AMD senior vice president, Corporate Fellow, and Product Technology Architect. Naffziger works across the company to optimize product technology choices and deployment with a continued focus on driving best practice power/performance/area methodology to maximize product competitiveness, efficiency, and cost. Naffziger has been the lead innovator behind many of AMD’s low-power features and chiplet architecture. He has over 32 years of industry experience with a background in microprocessors and circuit design at Hewlett Packard, Intel and AMD. Naffziger received a Bachelor of Science degree in Electrical Engineering from the California Institute of Technology (CalTech) and a Master of Science from Stanford. Naffziger holds more than 130 U.S. patents in the field and authored dozens of publications and presentations on processors, architecture and power management. He is an IEEE Fellow.
Keynote II: April 27, 2021 9:00am – 9:50am CDT
Title: Mixed Signal Designs for A Digitized World
Vida Ilderem, Vice President & Director Wireless Systems Research, Intel Corporation
Abstract: Our physical world’s digital representation continues to grow at a fast pace, resulting in the generation of large amounts of data of various types. While ‘5G and beyond’ network transformation is still ramping, we expect their deployment to accelerate, especially in the post-pandemic era. The proliferation of sensors and intelligent machines – and their low-latency requirements – are motivating a shift of computing to edge networks, closer to these devices and the data they generate. Data sources are also becoming increasingly distributed and mobile. This presentation will cover some of the innovations/opportunities and the role of RF/Analog mixed signal designs to enable this digitized world.
Speaker’s Bio: Dr. Vida Ilderem is Vice President and director of Wireless Systems Research (WSR) at Intel Labs. WSR explores breakthrough wireless technologies to fulfill the promise of secure, energy efficient, seamless and affordable connection and sensing for people and things. Prior to joining Intel in 2009, Vida served as vice president of Systems and Technology Research at Motorola’s Applied Research and Technology Center, where she was also recognized as Motorola Distinguished Innovator. Vida holds a doctorate and a master’s degree in electrical engineering from Massachusetts Institute of Technology, a bachelor’s degree in electrical engineering and a bachelor’s degree in physics from California State University, Fresno. She has 27 issued patents and has given numerous invited talks and keynotes at IEEE and other venues on nanotechnology, RF, IoT & Wearables, 5G/5G+, and innovation.
Keynote III: April 29, 2021 9:00am – 9:50am CDT
Title: The Future of Memory Chip Technology
Gurtej S Sandhu, Senior Fellow and Vice President, Micron Technology Inc.
Abstract: Without advances in how the world physically stores and retrieves data, today’s most useful devices and algorithms would not exist. The dominant memory chip technologies such as NAND Flash and DRAM rode the wave of innovations in materials, process and device technologies to scale down the path of Moore’s law. Although physical scaling is becoming increasingly difficult, the forces and market pull driving cost, power and density scaling are growing relentlessly. The amount of memory in systems for example is increasing geometrically while the power budget continues to decrease. In addition, the applications and resultant memory requirements continue to diversify and expand from traditional handheld devices and large data centers. A commitment to innovation and creativity at a system level design is required to meet demands of the data age. These innovations will help fuel the next generation of technologies such as self-driving cars, space exploration, artificial intelligence and machine learning, which sounded like science fiction not so long ago. Several technologies have been proposed over the years with no clear winner. Some of the critical factors which need to be considered for a successful implementation of a new technology include; why and when alternate memory technologies may be needed, what are the performance criteria and requirements, and what needs to happen in the ecosystem to support a successful new technology. The result of this reality is that bottoms up development for a new memory technology may not be feasible due to technical risks and cost and we must target application-specific solutions for new markets.
Speaker’s Bio: Gurtej Sandhu is Senior Fellow and Vice President at Micron Technology. In his current role, he is responsible for Micron’s end-to-end (Si-to-Package) R&D technology roadmaps. The scope includes driving cross-functional alignment across various departments and business units to proactively identify technology gaps and managing the engineering organization to resource and execute on developing innovative technology solutions for future memory scaling. Dr. Sandhu’s responsibilities include leading several internal project teams worldwide and managing interactions with research consortia around the world. At Micron, Dr. Sandhu has held several engineering and management roles and is actively involved with a broad range of process technologies and has pioneered several process technologies currently employed in mainstream semiconductor chip manufacturing. Dr. Sandhu received a degree in electrical engineering at the Indian Institute of Technology, New Delhi, and a Ph.D. in physics at the University of North Carolina, Chapel Hill, in 1990. He holds over 1,300 U.S. patents and is recognized as one of the top inventors in the world. A Fellow of IEEE, in 2018, he received the prestigious IEEE Andrew S. Grove Award for outstanding contributions to solid-state devices and materials technology, as well as for leadership, originality, breadth, incentive value, publications, among other achievements. This competitive award is presented annually by the IEEE Board of Directors to an individual with pioneering achievements to the semiconductor materials technology.
Keynote IV: April 30, 2021 9:00am – 9:50am CDT
Title: Semiconductor Technology – The Path Forward for The Coming Decades
H.-S. Philip Wong, Willard R. and Inez Kerr Bell Professor of Electrical Engineering Stanford University
Abstract: The semiconductor industry has been extremely successful in integrating discrete components into billion-transistor chips. Future electronic systems will continue to rely on, and increasingly benefit from, the advances in semiconductor technology as they have had for more than five decades. Applications such as AI, machine learning, 5G, and even quantum computing, will not fulfill their promises without the continual advancements of semiconductor technology that is anticipated. 21st century applications are going to be data-centric. Data analytics, machine learning, and AI applications are going to dominate, from data center to mobile and IoT, from collecting and processing, to curating the data to derive information. Many systems will need to learn and adapt on the fly. The emergence of abundant-data computing made the system throughput and system throughput/Watt the key performance metrics. These metrics can be improved by more and more specialization from CPU to GPU, to TPU and accelerators that are able to execute a narrow set of tasks in a massively parallel fashion. In other words flexibility has been traded off to maximize system throughput and energy efficiency. Computation throughput has been advancing faster than the memory bandwidth, resulting in a bandwidth deficit that limits system performance. With this in mind, this presentation will look at how the performance of those specialized architectures can be improved at the system level by advances of the underlying device and process technologies. An analysis of the technology trend for GPU and accelerators leads to a key observation: in the coming decades, we must go beyond a single chip from a wafer and focus on integrating chips into systems.
Speaker’s Bio: H.-S. Philip Wong is the Willard R. and Inez Kerr Bell Professor in the School of Engineering at Stanford University. He joined Stanford University as Professor of Electrical Engineering in September, 2004. From 1988 to 2004, he was with the IBM T.J. Watson Research Center. From 2018 to 2020, he was on leave from Stanford and was the Vice President of Corporate Research at TSMC, the largest semiconductor foundry in the world. Since 2020, he has been the Chief Scientist of TSMC. He is a Fellow of the IEEE and received the IEEE Electron Devices Society J. J. Ebers Award for “pioneering contributions to the scaling of silicon devices and technology.” Prof. Wong and his students have won best paper awards at premier conferences such as the International Solid-State Circuits Conference (ISSCC) and Symposia on VLSI Technology and Circuits. He served as General Chair of the International Electron Devices Meeting (IEDM), subcommittee chair of the ISSCC, and is currently the Chair of the IEEE Executive Committee of the Symposia on VLSI Technology and Circuits. He is the founding Faculty Co-Director of the Stanford SystemX Alliance – an industrial affiliate program focused on building systems, and the faculty director of the Stanford Non-Volatile Memory Technology Research Initiative (NMTRI).