CICC

2020 CICC Educational Sessions

Educational Sessions

Sunday, 22 March

Educational Sessions are held on Sunday, March 22nd all-day. Attendance to any of them is included in the standard conference registration. Take this opportunity to learn about new topics from leading engineers in the field.

 

Abstract and Bios for the Speakers and Sessions can be found below.

 

Educational Session 1 –RF/mmW Power Amplifiers

Chair: Debo Chowdhury

ES1-1. Peter Asbeck, UCSD Bio | Abstract
–Title: High Efficiency mm-Wave Power Amplifiers in CMOS-SOI and SiGe for 5G

ES1-2. Saeid Daneshgar, Intel
–Title: High Power Generation for mm-Wave 5G Power Amplifiers in Deep Submicron Planar and FinFET Bulk CMOS

ES1-3. Sangmin Yoo, Michigan State University
–Title: Digital Power Amplifiers and Transmitters Based on RF Digital-to-Analog Converter

ES1-4. Johanna Yan, Maxentric
–Title: Envelope Tracking for 5G and mm-wave Power Amplifiers

Educational Session 2 – Phase-Locked Loops

Chair: Woogeun Rhee

ES2-1. Robert Staszewski, University College Dublin, Ireland
– Title: Beyond All-Digital PLL for RF and Millimeter-Wave Frequency Synthesis

ES 2-2. Sudhakar Pamarti, UCLA
– Title: Basics of Closed- and Open-Loop Fractional Frequency Synthesis

ES 2-3. Mike Shuo-Wei Chen, USC
– Title: Low-Spur PLL Architectures and Techniques

ES 2-4. Nereo Markulic, IMEC, Leuven, Belgium
– Title: Digital-to-Time Converter-based Subsampling PLLs for Frequency Synthesis and Phase Modulation

Educational Session 3 – Transceivers (5G /IoT)

Chair: Yanjie Wang

ES3-1. Jongwoo Lee, Samsung
– Title: 5G RF transceiver design for EN-DC and mmWave

ES3-2. Zhihua Wang, Tsinghua University
– Title: Design of RF transceivers for medical applications in 5G/IoT era

ES3-3. Jerald Yoo, National University of Singapore
– Title: Body Area Network – Connecting Things Together Around the Human Body

ES3-4. Brian Ginsburg, Texas Instruments
– Title: Fundamentals of Modern mmW Radars

Educational Session 4 – Data Converters and Interface Circuits

Chair: Nan Sun

ES4-1. Nima Maghari, University of Florida
– Title: Backend Improvement in ΔΣ ADCs

ES4-2. Ben Hershberg, Oregon State University
-Title: Ringamp: The Scalable Amplifier We’ve All Been Waiting For?

ES 4-3. Gabriele Manganaro, Analog Devices Inc.
-Title: High Speed Digital-to-Analog Converters – A tutorial

ES4-4. Ross Walker,  University of Utah
-Title: Analog front-ends for large scale neural recording

Educational Session 5 – MathWorks Sessions

ES5-1. Idin Motedayen-Aval, Applications Engineer, MathWorks
-Title: Top-Down Design for Mixed-Signal Circuits

This session will provide an introduction to using Simulink for behavioral simulation of analog/mixed-signal devices. We will provide a brief tutorial on the tool and its interface, and then explore mixed-signal examples. The talk will also cover connections to downstream circuit design tools.

  • Tutorial on Simulink for feedback control systems
  • Top-Down Design for Mixed-Signal
  • Examples
    • ADC
    • PLL
  • Connections to EDA Tools
    • Co-simulation between Simulink and other analog simulators
    • Exporting DPI-C (SystemVerilog) models

ES5-2. Mike Mayer, Applications Engineer, MathWorks
-Title: Introduction to IBIS-AMI

The speed of serial communication links (SerDes) continues to climb, and design complexity grows with it. IBIS-AMI models are a standardized way for SerDes designers to share a behavioral model of their chip with downstream system designers such as board-level signal integrity engineers. Creating IBIS-AMI models is now part of the workflow for SerDes designers, but it is a complex and time consuming task which requires knowledge of the IBIS-AMI specification, SerDes, signal integrity, and C programming. This talk covers the background of IBIS-AMI, the basics of the specification, and approaches to generating standard models more efficiently.

  • What is IBIS and IBIS-AMI?
  • Why behavioral models?
  • IBIS History
  • IBIS-AMI for SerDes
  • IBIS-AMI for DDR5
  • Creating IBIS-AMI models
  • Using IBIS-AMI models

Educational Session 1 –RF/mmW Power Amplifiers

Chair: Debo Chowdhury

ES1-1. Peter Asbeck, UCSD
–Title: High Efficiency mm-Wave Power Amplifiers in CMOS-SOI and SiGe for 5G

Abstract: 5G NR waveforms pose significant challenges for power amplifiers, as a result of their high peak-to-average power ratios, high bandwidths and requirements for low EVM – without the use of digital predistortion. CMOS-SOI and SiGe HBT technologies can attain the output power levels needed for most 5G mm-wave applications (Psat to above 23dBm). This talk will review device considerations impacting power and efficiency of mm-wave PAs, and presents 5G amplifier designs using Doherty, outphasing and hybrid designs to increase efficiency to above 25% at 6dB backoff. Design techniques for integration of PA, LNA and switches for mm-wave front-ends are also discussed.

ES1-2. Saeid Daneshgar, Intel
–Title: High Power Generation for mm-Wave 5G Power Amplifiers in Deep Submicron Planar and FinFET Bulk CMOS

Abstract: The required output power of power amplifiers (PAs) in 5G mm-Wave wireless transmitters is estimated to vary in the range of 18 to 24dBm across handset, access point, base station, and backhaul applications. A common perception within the industry is that at such power levels, low-cost bulk CMOS is inadequate in efficiency and there is a need for specialized technologies such as SOI or GaN. This tutorial attempts to allay such concerns and presents the key techniques for high power, high efficiency mm-Wave 5G PA design in deep submicron planar and FinFET bulk CMOS processes. It covers the design steps of reliable high power generation all the way from transistor level layout to active and passive on-chip power combining followed by a prediction of saturated output power (Psat) and its corresponding maximized power added efficiency (PAE) for a 3-stage PA. Finally, the tutorial will conclude with the measured results of two 39GHz PA prototypes in 16nm FinFET and 28nm planar bulk CMOS processes.

ES1-3. Sangmin Yoo, Michigan State University
–Title: Digital Power Amplifiers and Transmitters Based on RF Digital-to-Analog Converter

Abstract: In the era of the internet of things (IoT) and 5G communication, small, linear, and power-efficient wireless power amplifiers (PAs) and transceivers are critical for the small form factor, high-data throughput, and extended battery life of many mobile devices. On the other hand, innovations in analog/RF circuits have been driven by rapidly-evolving semiconductor technology in line with Moore’s law. Digital PA and transmitter (Tx), based on RF digital-to-analog converter (DAC) architecture, have shown great promises for Tx systems with small area and excellent energy efficiency. The digital PA and Tx architecture, mostly based on digital circuits and switches, directly benefits from the advances in state-of-the-art nanometer-scale CMOS technology. The future of digital PA/Tx in wireless systems is not far away. This talk will give an introduction to the digital PA, and also cover recent advances, directions, and benefits that the wireless digital PA/Tx will bring about. Recent design examples will also be discussed. A polar switched-capacitor (SC) digital PA with 30dBm peak POUT demonstrates several efficiency peaks down to 18dB power backoff (PBO) associated with efficiency boosting techniques such as class-G, Doherty, and time-interleaving. A complete quadrature SC digital Tx with 13dBm peak POUT demonstrates a very small area and a low power consumption. These recent digital PA and digital Tx prototypes also show a great linearity of <-40dB EVM over >20dB POUT range without any digital predistortion (DPD) for an 802.11 signal.

ES1-4. Johanna Yan, Maxentric
–Title: Envelope Tracking for 5G and mm-wave Power Amplifiers

Abstract: The demand for high data rates and better throughput has driven 5G communication systems to use higher order modulations. To overcome the efficiency degradation in power amplifiers in the presence of such waveforms, advance power amplifier architectures are needed. Among them is the envelope tracking power amplifier (ETPAs). In this talk, ETPAs based on both analog and digital modulators will be described and compared. Analog modulators, with hybrid architectures of different switching and linear stages in parallel and series configurations, and digital modulators, producing envelope approximates use as power DACs, multi-switchers, or tap-changers, are compared in terms of their performance merits (waveform fidelity, bandwidth, efficiency, etc), with emphasis on 5G applications. ETPAs designs and considerations for enabling digital communication systems with multi-beam/multi-channel transmission will be discussed. Linearization techniques for both analog and digital ETPAs and multi-beam/multi-channel operation will be shown.

Educational Session 2 – Phase-Locked Loops

Chair: Woogeun Rhee

ES2-1. Robert Staszewski, University College Dublin, Ireland
– Title: Beyond All-Digital PLL for RF and Millimeter-Wave Frequency Synthesis

Abstract: The past several years has seen proliferation of all-digital phase-locked loops (ADPLL) for RF, mm-wave and high-performance frequency synthesis due to their clear benefits of flexibility, reconfigurability, transfer function precision, settling speed, frequency modulation capability, and amenability to integration with digital baseband and application processors. When implemented in nanoscale CMOS, the ADPLL also exhibits advantages of better performance, lower power consumption, lower area and cost over the traditional analog-intensive charge-pump PLL. In a typical ADPLL, a traditional VCO got directly replaced by a digitally controlled oscillator (DCO) for generating an output variable clock, a traditional phase/frequency detector and a charge pump got replaced by a time-to-digital converter (TDC) for detecting phase departures of the variable clock versus the frequency reference (FREF) clock, and an analog loop RC filter got replaced with a digital loop filter. The conversion gains of the DCO and TDC circuits are readily estimated and compensated using ‘free’ but powerful digital logic. After covering the fundamentals of ADPLL, the tutorial will venture into the future of RF and mm-wave frequency synthesis: charge-sharing locking (CSL). The idea is that the capacitor of the LC tank itself will be periodically charge-shared with another capacitor charged by a DAC to a voltage that is expected from a waveform at that particular time point, resulting in an instantaneous phase correction. The resulting voltage change will be detected and used to correct the DCO frequency. This results in a great simplification of circuitry and consumed power while delivering sub-100fs integrated jitter.

Bio: R. Bogdan Staszewski received B.Sc. (summa cum laude), M.Sc. and PhD from University of Texas at Dallas, USA, in 1991, 1992 and 2002, respectively. From 1991 to 1995 he was with Alcatel in Richardson, Texas. He joined Texas Instruments in Dallas, Texas in 1995. In 1999 he co‐started a Digital RF Processor (DRP) group in TI with a mission to invent new digitally intensive approaches to traditional RF functions. Dr. Staszewski served as a CTO of the DRP group between 2007 and 2009.

ES 2-2. Sudhakar Pamarti, UCLA
– Title: Basics of Closed- and Open-Loop Fractional Frequency Synthesis

Abstract: Fractional frequency synthesis is employed in a wide variety of applications, and the circuits that realize fractional frequency synthesis come in several forms. This talk presents the basics of fractional frequency synthesis by roughly grouping them into closed loop approaches such as those based on phase locked loops, and open loop approaches such as those based on fractional dividers and digital-to-phase converters. The talk will describe how these systems work, focusing on commonalities such as the use of digital delta sigma modulators, and on unique differences. The talk will also explore metrics such as phase noise, jitter, and spurious tones in these systems using examples wherever appropriate.

Bio: Sudhakar Pamarti is a Professor of Electrical and Computer Engineering at the University of California, Los Angeles. He received the Bachelor of Technology degree from the Indian Institute of Technology, Kharagpur in 1995, and the Ph.D. degrees in electrical engineering, specializing in fractional frequency synthesis, from the University of California, San Diego in 2003. His current research interests are in analog, mixed‐signal, and RF integrated circuit design, specifically in developing signal processing techniques to overcome circuit impairments. He has, in the past, worked for both software and hardware companies, and regularly engages with the integrated circuit design industry in a technical advisory role. Dr. Pamarti was a recipient of the National Science Foundation’s CAREER award. He currently serves on the technical program committees of IEEE Custom Integrated Circuits Conference and IEEE International Solid State Circuits Conference, and has, in the past, served as an Associate Editor for both Parts I and II of the IEEE Transactions on Circuits and Systems.

ES 2-3. Mike Shuo-Wei Chen, USC
– Title: Low-Spur PLL Architectures and Techniques

Abstract: One key design objective of a frequency synthesizer is to minimize the spurious tones, as they can degrade the overall jitter performance or cause other unwanted system-level impairments. In this tutorial, we will examine the sources of the spurious tone generation in different PLL architectures and operation modes. We will overview several design techniques to mitigate the spurious tones. Lastly, we will go over several real PLL design examples that demonstrate low-spur performances.

Bio: Mike Shuo‐Wei Chen received the B.S. degree from National Taiwan University, Taipei, Taiwan, in 1998 and the M.S. and Ph.D. degree from University of California, Berkeley, in 2002 and 2006, all in electrical engineering. He is an associate professor in Electrical Engineering Department at University of Southern California (USC) and holds Colleen and Roberto Padovani Early Career Chair position.

ES 2-4. Nereo Markulic, IMEC, Leuven, Belgium
– Title: Digital-to-Time Converter-based Subsampling PLLs for Frequency Synthesis and Phase Modulation

Abstract: The tutorial starts with a basic/introductive overview of modern frequency synthesis techniques, delivering basic operation theory in an intuitive fashion. A point of attention is in this context brought to recent subsampling PLL architecture. This architecture overcomes the performance boundaries typically encountered in classical implementations and is redefining today’s state-of-the state of art in frequency synthesis. We will try to explain why. The following part of the tutorial explores the subsampling loop in context of state-of-the art fractional synthesis and phase modulation. We show how to enable fractional-N multiplication modes, while retaining benefits of low-noise subsampling operation. This can be achieved by introducing digital-to-time converter (DTC)-based time domain signal processing. We will discuss potential limitations of this block, and how to overcome them in the analog, or in the digital domain. The versatility of the DTC-based subsampling PLL will further be discussed in context of phase/frequency modulation, which is crucial for accurate polar signaling. We will investigate classical loop-bandwidth limitations and explore how two-point modulation principles can elegantly be applied in context of the explored loop. We will openly discuss potential weak-points of this environment – and how to address them. This talk insists on an intuitive, rather than a strict, mathematical approach to PLLs. It starts from the basic concepts and then gradually expands in complexity, while clearly highlighting the key ideas and pointing to state-of-the-art embodiments.

Bio: Nereo Markulic received M.Sc. degree (2012) in electrical engineering from University of Zagreb, Croatia and a Ph.D. degree (2018) summa cum laude from Vrije Universiteit Brussel, Belgium. His Ph.D. work was in collaboration with imec, Belgium on digital subsampling PLLs and Polar Transmitters. He is currently a research scientist in imec, Belgium, working on mixed‐signal circuits for radar applications and next generation wireless communication. He has authored and co‐authored several publications and patents on PLLs and analog‐to‐digital converters, a book on frequency synthesis and is a co‐recipient of ISSCC 2019 Lewis Winner Award for Outstanding Paper.

Educational Session 3 – Transceivers (5G /IoT)

Chair: Yanjie Wang

ES3-1. Jongwoo Lee, Samsung
– Title: 5G RF transceiver design for EN-DC and mmWave

ES3-2. Zhihua Wang, Tsinghua University
– Title: Design of RF transceivers for medical applications in 5G/IoT era

Abstract: In the upcoming 5G era, mobile communication system can provide extremely high speed, extremely low latency, and almost unlimited addresses for everything in the universe. On the other hand, with the aging of the population and the improvement of people’s living standards, the requirements for health and medical care are becoming more and more urgent and effective. The demand of medical electronic devices, which is one of the important types of IoT in 5G era, to make the medical devices smaller and smarter, will be one of the driving force of integrated circuits and systems. The implantable medical devices (IMD’s), which are fully or partially implanted in the human bodies through surgeries, have a series of strict technical requirements including the choice of frequency and bandwidth, low power consumption, data rate, signal modulation method, disturbing and interference etc. This lecture focuses on a recently proposed technique in the art of radio transceiver design to reduce power consumption and area occupation. A set of miniature IMD’s have been implemented using this ultra-low power transceiver which can be integrated in different application specific systems-on-a-chip (SoC’s).

Bio: Zhihua Wang (M’99‐SM’04‐F’17) received the B.S., M.S., and Ph.D. degrees in Electronic Engineering in 1983, 1985 and 1990, respectively, from Tsinghua University, Beijing, China, where he has been a full professor in the Institute of Microelectronics since 1997. He was a visiting scholar at CMU (1992‐1993) and KU Leuven (1993‐1994), and was a visiting professor at HKUST (2014.9‐2015.3). His current research mainly focuses on CMOS RFIC and biomedical applications, involving RFID, PLL, low‐power wireless transceivers, and smart clinic equipment combined with leading edge RFIC and digital image processing techniques. He has co‐authored 13 books/chapters, over 209 (537) papers in international journals
(conferences), over 249 (29) papers in Chinese journals (conferences) and holds 122 Chinese and 9 US patents. Prof. Wang has served as the chairman of IEEE SSCS Beijing Chapter (1999‐2009), an AdCom Member of the IEEE SSCS (2016‐2019), a technology program committee member of the IEEE ISSCC
(2005‐2011), a steering committee member of the IEEE A‐SSCC (2005‐), the technical program chair for A‐SSCC 2013, a guest editor for IEEE JSSC Special Issues (2006.12, 2009.12 and 2014.11), IEEE SSCS Distinguished Lecturer(2018‐2019), IEEE CASS Distinguished Lecturer(2020‐2021), Associate Editors in Chief, IEEE Open Journal of Circuits and Systems (2019~), associate editor of IEEE Trans on CAS‐I, II and IEEE Trans on BioCAS, and other administrative/expert committee positions in China’s national science and technology).

ES3-3. Jerald Yoo, National University of Singapore
– Title: Body Area Network – Connecting Things Together Around the Human Body

Abstract: Body Area Network (BAN) provides an attractive means for continuous and pervasive health monitoring, yet its unique and harsh environment gives circuit designers many challenges. As human body absorbs the majority of RF energy around GHz band, existing RF radio may not be an ideal for communications between and on-body sensors. In order to solve the issues, this education session talk presents the Body Coupled Communication (BCC)-based BAN. The BCC BAN utilizes human body itself as a communication medium, which has orders of magnitude less pathloss when compared to RF based BAN. We will cover three types of BCC-BAN: 1) capacitive coupling, 2) magnetic coupling and 3) galvanic coupling. For each type, we will explorer its channel characteristics followed by design considerations and transceiver implementation examples. I will then discuss what circuit designers should consider in such non-conventional environments. Low energy circuit techniques to overcome their limitations will also be discussed. We will then review their various system aspects of the BAN, including powering up the wearables using the wearable BAN.

Bio: Jerald Yoo received the B.S., M.S., and Ph.D. degrees in the Dept. of Electrical Engineering from the Korea Advanced Institute of Science and Technology (KAIST), Daejeon, Korea, in 2002, 2007, and 2010, respectively. From 2010 to 2016, he was with the Dept. of Electrical Engineering and Computer Science, Masdar Institute, Abu Dhabi, U.A.E., where he was an Associate Professor. From 2010 to 2011, he was also with the Microsystems Technology Laboratories (MTL), Massachusetts Institute of Technology (MIT) as a visiting scholar. Since 2017, he has been with the Dept. of Electrical and Computer Engineering, National University of Singapore, Singapore, where he is currently an Associate Professor.

ES3-4. Brian Ginsburg, Texas Instruments
– Title: Fundamentals of Modern mmW Radars

Abstract: mm-Wave radars are a key sensor for modern automotive driver assistance systems and have emerging uses in building and factory automation, as well as human interactive motion sensing.  This tutorial will cover the basic radar parameters including resolution, accuracy, and maximum range, and show how those are linked to fundamental system specifications.  Frequency modulated continuous wave (FMCW) is the dominant waveform.  Detailed examples will be given of a fast chirp FMCW implementation.  Finally, recent radar advances, including PMCW modulation, imaging radars, and integrated antennas will be discussed.

Bio: Brian Ginsburg received his S.B., M.Eng., and Ph.D. degrees from the Massachusetts Institute of Technology. He joined Texas Instruments, Dallas, Texas in 2007 working in its wireless terminals business unit and TI’s Kilby Labs. Now, he is a Distinguished Member of Technical Staff and the systems manager of TI’s radar business. He has served on the technical program committee for the International Solid‐State Circuits Symposium and is the Program Chair of the 2020 Symposium on VLSI Circuits

Educational Session 4 – Data Converters and Interface Circuits

Chair: Nan Sun

ES4-1. Nima Maghari, University of Florida
– Title: Backend Improvement in ΔΣ ADCs

Abstract: Delta-Sigma modulators are widely used in applications ranging from low frequency and audio to wideband wireless receivers. Several key advantages such as anti-aliasing filtering, reduced sensitivity to some circuit non-idealities such as lowered opamp gain requirement, wide dynamic range among others have contributed to the success of these structures. However, as the move towards higher data rates and wide bandwidth is becoming more dominant, the limiting factor of delta-sigma ADCs becomes the achievable sampling speed to maintain the efficiency of the oversampling ratio. Consequently, comprehensive efforts have been dedicated in improving the backend quantization and excess loop delay compensation in the past decade leading to various innovations in circuit and system level. However, a comprehensive study of the behavior, the advantages and drawbacks of these techniques is missing from the literature and textbooks. In this talk, the effects of back-end quantizer in ΔΣ ADCs are discussed in details, the new emerging quantizers and excess loop-delay compensation schemes are presented and the advantages and drawbacks of each will be analyzed.

Bio: Nima Maghari received the B.S. degree in electrical engineering from the University of Tehran, Iran, in 2004 and the Ph.D. degree in electrical engineering from Oregon State University in 2010. He is currently an associate professor at the school of electrical and computer engineering, University of Florida, Gainesville. From 2004 to 2006, he was with IC‐LAB, University of Tehran, where he was involved with audio delta‐sigma converters and low‐voltage bandgap references. In 2008 he was recipient of CICC‐AMD outstanding student paper award. He has served as an Associated Editor of IEEE Transactions on Circuits and Systems‐I and the technical program committee of IEEE CICC as Data Converter Sub‐Committee Chair. He is on the editorial board of Journal of Solid‐State Circuit Letters and IET Electronics Letters. He has published more than 60 conference and journals papers in IEEE and IEE. His research interests include high performance analog‐to‐digital converters, delta‐sigma modulators, synthesizable analog circuits, time‐assisted data conversion techniques, low‐power low‐voltage regulators, and analog security and counterfeit detection.

ES4-2. Ben Hershberg, Oregon State University
-Title: Ringamp: The Scalable Amplifier We’ve All Been Waiting For?

Abstract: Conventional opamps have not scaled gracefully into nanoscale CMOS, and the quest for a general-purpose replacement continues to challenge the research community. This has fundamentally reshaped the field of ADCs in the last decade, where designers have been forced toward architectures that avoid linear amplifiers as much as possible. This evolutionary pressure has in many ways been a boon, stimulating new approaches and ways of thinking. But it also raises the question: what opportunities for creativity and innovation did we lose when we left opamps behind? What impact would a viable successor have on the ADC landscape? Ring amplification is an emerging technique that offers the possibility of high efficiency, high performance, scalable, and general-purpose switched capacitor amplification. This talk will begin with a discussion of what exactly a “ringamp” is, how it works, and why it works so well. We will then go through a practical design example and see how the modelling and validation process is fundamentally different from conventional opamp design. We will also consider challenges such as PVT robustness. With a foundation in place, we will expand to considerations of topology choices and performance enhancements that can be used to build the optimal ringamp for a given application.

Bio: Benjamin Hershberg earned his Ph.D. from Oregon State University in 2012, introducing the idea of ring amplification at ISSCC that same year. Since 2013 he has been at imec in Leuven, Belgium conducting research on a variety of topics encompassing the full receiver chain, from the antenna down to the ADC. His obsession with ringamps still continues today, and his current research interests include tackling the final challenges of industrialization and looking for opportunities to use ringamps to solve open challenges in ADCs.

ES 4-3. Gabriele Manganaro, Analog Devices Inc.
-Title: High Speed Digital-to-Analog Converters – A tutorial

Abstract: Current-steering Digital-to-Analog Converters (DACs) are commonly the architecture of choice for analog signal synthesis from MHz to sub-THz frequencies in a variety of applications ranging from wireless and wired communication, instrumentation, imaging to defense among others. This tutorial will guide the audience from the basic architectural concepts and simplest circuit implementations to the different types of impairments and ways to mitigate them. Trade-offs, circuits and layout techniques to overcome them, and examples of actual high-speed DACs embodying the different concepts will be discussed in a intuitive fashion, providing the audience with selected literature references for deepening the material as needed.

Bio: Gabriele Manganaro (S’95, M’98, SM’03, F’16) holds a Dr.Eng. and a Ph.D. degree in Electronics from the University of Catania, Italy. Starting in 1994, he did research at ST Microelectronics and at Texas A&M University. He worked in data converters’ IC design at Texas Instruments, Engim Inc, and eventually as Design Director at National Semiconductor. Since 2010 he has been with Analog Devices, first as an Engineering Director for High Speed Data Converters, and more recently as a Technology Director in the Wireless Communication Products Division. He served in the technical sub‐committee for Data Converters of the ISSCC for seven consecutive years. He was Associate Editor for IEEE Trans. On Circuits and Systems ‐ Part II and then Associate Editor, Deputy Editor in Chief and finally Editor in Chief for IEEE Trans. On Circuits and Systems ‐ Part I. He is presently the Editor in Chief for the IEEE Open Journal of Circuits and Systems. He authored/co‐authored more than 60 peer‐reviewed papers, three books
(notably “Advanced Data Converters”, Cambridge University Press, 2011) and has been granted 17 US patents, with more pending. He was recipient of scientific awards, including the 1995 CEU Award from the Rutherford Appleton Laboratory (UK), the 1999 IEEE Circuits and Systems Outstanding Young Author Award and the 2007 IEEE European Solid‐State Circuits Conference Best Paper Award. He is an IEEE Fellow (since 2016), a Fellow of the IET (since 2009), Member of the scientific honor society Sigma Xi, and was a member of the Board of Governors for the IEEE Circuits and Systems Society (2016‐18). He is a Distinguished Lecturer for the IEEE Solid‐State Circuits Society (term 2019‐20) and an industry advisory member for Proceedings of the IEEE. Gabriele has received international technical & leadership recognition; he is often invited to speak on technical subjects at key conferences and top universities and developed and taught graduate professional courses in data converters design and mixed‐signal design at the University of Oxford (UK).

ES4-4. Ross Walker,  University of Utah
-Title: Analog front-ends for large scale neural recording

Abstract: In the last 60 years, microfabrication techniques developed for ICs have driven exponential growth in the number of individual brain cells that can be recorded from simultaneously, albeit with a shallower slope compared to Moore’s law (doubling every ~7 years). At the current state of the art, analog front-ends for neural recording have become a major bottleneck in understanding the brain, and are also seen as a limitation for potential human applications of large scale neural interfacing. This tutorial will first review established solutions for signal conditioning and data conversion in neural recording, including both architecture and circuit implementation. New techniques that march the data converter closer to the electrode sites will be presented and analyzed, including direct delta-sigma conversion and rapidly multiplexed Nyquist approaches. Tradeoffs in power, area, and system complexity will be highlighted, as well as application specific design criteria that motivate further innovation.

Bio: Ross M. Walker (S’08–M’13) received B.S. degrees in electrical engineering and computer science from the University of Arizona, Tucson, AZ, USA, in 2005 and the M.S. and Ph.D. degrees in electrical engineering from Stanford University, Stanford, CA, USA, in 2007 and 2013, respectively. His Ph.D. research, which was advised by Prof. Boris Murmann, focused on IC design for large scale neural recording. As a student, he worked as an Intern at International Business Machines, Tucson, AZ, USA, and Linear Technology (now Analog Devices), Milpitas, CA, USA. Since 2013, he has been with the Department of Electrical and Computer Engineering, University of Utah, Salt Lake City, UT, USA, where he currently serves as Associate Professor. His research interests include electronic circuits and systems, with an emphasis on neuroscience and neural engineering applications. Prof. Walker is a past chair of the Utah Solid State Circuits Society Chapter (2017‐2019), and currently serves on the Board of Governors of the IEEE Circuits and Systems Society as well as the IEEE Biomedical and Life Science Circuits and Systems Technical Committee.

Educational Session 5 – MathWorks Sessions

ES5-1. Idin Motedayen-Aval, Applications Engineer, MathWorks
-Title: Top-Down Design for Mixed-Signal Circuits

This session will provide an introduction to using Simulink for behavioral simulation of analog/mixed-signal devices. We will provide a brief tutorial on the tool and its interface, and then explore mixed-signal examples. The talk will also cover connections to downstream circuit design tools.

  • Tutorial on Simulink for feedback control systems
  • Top-Down Design for Mixed-Signal
  • Examples
    • ADC
    • PLL
  • Connections to EDA Tools
    • Co-simulation between Simulink and other analog simulators
    • Exporting DPI-C (SystemVerilog) models

ES5-2. Mike Mayer, Applications Engineer, MathWorks
-Title: Introduction to IBIS-AMI

The speed of serial communication links (SerDes) continues to climb, and design complexity grows with it. IBIS-AMI models are a standardized way for SerDes designers to share a behavioral model of their chip with downstream system designers such as board-level signal integrity engineers. Creating IBIS-AMI models is now part of the workflow for SerDes designers, but it is a complex and time consuming task which requires knowledge of the IBIS-AMI specification, SerDes, signal integrity, and C programming. This talk covers the background of IBIS-AMI, the basics of the specification, and approaches to generating standard models more efficiently.

  • What is IBIS and IBIS-AMI?
  • Why behavioral models?
  • IBIS History
  • IBIS-AMI for SerDes
  • IBIS-AMI for DDR5
  • Creating IBIS-AMI models
  • Using IBIS-AMI models