CICC

Educational Sessions

2021 CICC Educational Sessions

Educational Sessions

Sunday, 25 April

Educational Sessions are held on Sunday, April 25th all-day. Attendance to any of them is included in the standard conference registration. Take this opportunity to learn about new topics from leading engineers in the field.

Educational Session 1: Quantum Computing Circuit and System

9:00am-4:45pm CDT

Session Chairs: SungWon Chung, Neuralink, USA & Jongseok Park, Intel, USA

9:00am-11:00am CDT

ES1-1: Quantum Computing: What is it, how does it work, and why should circuit designers care?

Joseph Bardin, Google AI Quantum & University of Massachusetts Amherst, USA

ABSTRACT

As the field of quantum computing continues to grow, numerous opportunities will emerge for circuit designers to contribute. For instance, quantum processors are typically interfaced to using microwave control and readout, and, for the field to continue to succeed, these interfaces must be simplified and integrated. In this talk, I will provide an introduction to quantum computing and explain why circuit designers should be interested in the field. The talk will begin with a discussion of what quantum computation is and how it differs from regular digital (“classical”) computation. Once it is clear conceptually what we are trying to do, I will explain how one can systematically implement such a computational paradigm, focusing on superconducting qubit technology, but explaining how the concepts are relevant to other hardware implementations. Along the way, I will develop a picture of what control and measurement systems are required to run a quantum processor. The talk will end with a summary of the state of the art and a discussion of significant circuit related challenges that lie ahead.

BIO:

Joseph Bardin received the PhD degree in electrical engineering from the California Institute of Technology in 2009. In 2010, he joined the department of Electrical and Computer Engineering at the University of Massachusetts Amherst, where he is currently a Full Professor. His research group currently focuses on low temperature integrated circuits with applications in radio astronomy and the quantum information sciences. In 2017, he joined the Google AI Quantum team as a visiting faculty researcher and, in addition to his university appointment, he currently serves as a staff research scientist with this team. Professor Bardin was a recipient of a 2011 DARPA Young Faculty Award, a 2014 NSF CAREER Award, a 2015 Office of Naval Research YIP Award, a 2016 UMass Amherst College of Engineering Barbara H. and Joseph I. Goldstein Outstanding Junior Faculty Award, a 2016 UMass Amherst Award for Outstanding Accomplishments in Research and Creative Activity, and a 2020 IEEE MTT-S Outstanding Young Engineer Award

 

11:15am-12:45pm CDT

ES1-2: Cryo-CMOS Electrical Interfaces for Large-Scale Quantum Computers

Fabio Sebastiano, Delft University of Technology, Netherlands

ABSTRACT:

Quantum computers operate by processing information stored in quantum bits (qubits), which must typically operate at cryogenic temperature. Today the qubits are mostly controlled by conventional electronics working at room temperature. This thermal gap can be readily bridged by a few wires since today’s quantum computers employ only a few qubits. However, practical quantum computers will require more than thousands of qubits, making this approach impractical. A more scalable approach requires operating a complex electronic interface at cryogenic temperature, very close to the quantum processor, eventually in the same package or even on the same chip. Thanks to its high integration capabilities, CMOS is the most viable technology for such a cryogenic interface. In this talk, we will review the functionalities required to drive and control the most popular qubit technologies, and the requirements on the performance of the electronics, including a brief discussion of the modelling of the quantum/classical interface. Next, we will review the behavior of commercial CMOS devices and the available cryogenic device models required for circuit design. The demonstration of several state-of-the-art cryo-CMOS circuits and systems, both for qubit drive and readout, and their verification with qubits will be described, highlighting challenges and opportunities. Finally, the prospects towards large-scale quantum computers and towards qubit/electronics integration will be outlined.

BIO:

Fabio Sebastiano holds degrees in Electrical Engineering from University of Pisa, Italy (BSc, 2003; MSc, 2005) from Sant’Anna school of Advanced Studies, Pisa, Italy (MSc, 2006) and from Delft University of Technology, The Netherlands (PhD, 2011). From 2006 to 2013, he was with NXP Semiconductors Research in Eindhoven, The Netherlands. In 2013, he joined Delft University of Technology, where he is currently an Associate Professor. He has authored or co-authored one book, 11 patents, and over 70 technical publications. His main research interests are cryogenic electronics for quantum applications, sensor read-outs and frequency references. Dr. Sebastiano was the co-recipient of the best student paper award at ISCAS in 2008, the best paper award at IWASI in 2017 and the best IP award at DATE in 2018. He is a senior member of IEEE, a TPC member for RFIC and has served as Distinguished Lecturer of the IEEE Solid-State Circuit Society.

 

1:30pm-3:00pm CDT

ES1-3: Quantum Computing in Nanoscale CMOS Using Position-Based Charge Qubits

Robert Bogdan Staszewski, University College Dublin & Equal1, Ireland

ABSTRACT:

Quantum computing is a new paradigm that exploits fundamental principles of quantum mechanics, such as superposition and entanglement, to tackle problems in mathematics, chemistry and material science that are well beyond the reach of supercomputers. Despite the intensive worldwide race to build a useful quantum computer, it is projected to take decades before reaching the state of useful quantum supremacy. The main challenge is that qubits operate at the atomic level, thus are extremely fragile, and difficult to control and read out. The current state-of-art implements a few dozen magnetic-spin based qubits in a highly specialized technology and cools them down to a few tens of millikelvin. The high cost of cryogenic cooling prevents its widespread use. A companion classical electronic controller, needed to control and read out the qubits, is mostly realized with room-temperature laboratory instrumentation. This makes it bulky and nearly impossible to scale up to the thousands or millions of qubits needed for practical quantum algorithms. We propose a new quantum computer paradigm that exploits the wonderful scaling achievements of mainstream integrated circuits (IC) technology which underpins personal computers and mobile phones. Just like with a small IC chip, where a single nanometer-sized CMOS transistor can be reliably replicated millions of times to build a digital processor, we propose a new structure of a qubit realized as a CMOS-compatible charge-based quantum dot that can be reliably replicated thousands of times to construct a quantum processor. Combined with an on-chip CMOS controller, it will realize a useful quantum computer which can operate at a much higher temperature of 4 kelvin.

BIO:

Bogdan Staszewski received his PhD from University of Texas at Dallas, USA in 2002. He joined Texas Instruments in Dallas, Texas in 1995. In 1999 he co-started a Digital RF Processor (DRP) group in TI with a mission to invent new digitally intensive approaches to traditional RF functions. Dr. Staszewski served as a CTO of the DRP group between 2007 and 2009. In July 2009 he joined Delft University of Technology in the Netherlands. Since Sept. 2014 he is a Full Professor at University College Dublin (UCD) in Ireland. He has co-authored 120 journal and 200 conference publications, and holds 200 issued US patents. His research interests include nanoscale CMOS architectures and circuits for frequency synthesizers, transmitters and receivers, as well as quantum computers. He is a co-founder of a startup company Equal1 Labs aiming at building the first practical CMOS quantum computer. He is an IEEE Fellow and a recipient of IEEE Circuits and Systems Industrial Pioneer Award.

 

3:15pm-4:45pm CDT

ES1-4: Scaling Photonic Quantum Computers

Zachary Vernon & Blair Morrison, Xanadu Quantum Technologies, Canada

ABSTRACT:

Photonics is one of the most promising platforms for building and scaling quantum computing technology. Key advantages of the photonic approach include room-temperature operability of the core quantum processors, better compatibility with CMOS manufacturing processes, good overlap with optical telecommunications technology, and the ease with which quantum information can be transmitted over optical fiber. These advantages impact both the pace of development, enabling much faster R&D cycles when designing and scaling photonic processors, as well as the long-term prospects for how quantum computers will ultimately be used. In this presentation, we will give an overview of our efforts in leveraging silicon photonics to scale photonic quantum computing hardware, detailing the near-term hardware, as well as the long-term roadmap to error correction and fault-tolerance. This will be followed by a more detailed discussion of the development flows involved in the design, fabrication, testing, and systems-integration of photonic quantum processors.

BIO:

Zachary Vernon is the Head of Hardware at Xanadu, where he leads a team of over 20 physicists and engineers building the world’s first photonic quantum computers. Zachary holds a PhD in Physics from the University of Toronto and has expertise in integrated photonic technologies for generation, control, and measurement of quantum light.

 

 

 

Blair Morrison received a B.Sc. (Hons.) degree in physics from the Australian National University, Canberra, Australia, in 2010. He was with Dyesol, a solar research company focused on the development of dye solar cells, until the start of 2013. He then completed his PhD in nonlinear integrated microwave photonics at the end of 2017, at the Centre for Ultrahigh Bandwidth Devices for Optical Systems at the School of Physics, University of Sydney, Australia. Since 2018 he has worked on integrated photonic quantum computing hardware at Xanadu, where he currently leads the chip development team.

 

Educational Session 2: High Performance mm-wave Circuits

9:00am-4:45pm CDT

Session Chairs: Debo Chowdhury, Broadcom, USA & Hossein Miri Lavasani, Case Western Reserve University, USA

 

9:00am-10:30am CDT

ES2-1: Radio-frequency and Millimeter-Wave Phased Arrays

Hossein Hashemi, University of Southern California, USA

ABSTRACT:

Phased arrays enable electronic control of electromagnetic beam. There is a lot of interest in using phased arrays for commercial applications such as wireless communications (e.g., in the context of mm-wave beamforming for 5G), automotive radar, and imaging. This talk covers the phased array fundamentals, transceiver architectures, key enabling circuit building blocks at radio-frequency and millimeter-wave frequency ranges, and several case studies.

BIO:

Hossein Hashemi (M’99–SM’08–F’19) received the B.S. and M.S. degrees in electronics engineering from the Sharif University of Technology, Tehran, Iran, in 1997 and 1999, respectively, and the M.S. and Ph.D. degrees in electrical engineering from the California Institute of Technology, Pasadena, in 2001 and 2003, respectively. He is currently a Professor of electrical engineering, Ming Hsieh Faculty Fellow, and the Co-Director of the Ming Hsieh Institute, University of Southern California, Los Angeles, CA, USA. His research interests include electronic and photonic integrated circuits and systems. He was a recipient of the 2016 Nokia Bell Labs Prize, the 2015 IEEE Microwave Theory and Techniques Society (MTT-S) Outstanding Young Engineer Award, the 2008 Defense Advanced Research Projects Agency (DARPA) Young Faculty Award, the National Science Foundation (NSF) CAREER Award, and the USC Viterbi School of Engineering Junior Faculty Research Award in 2008. He was recognized as a Distinguished Scholar for the Outstanding Achievement in Advancement of Engineering by the Association of Professors and Scholars of Iranian Heritage in 2011.

 

10:45am-12:15pm CDT

ES2-2: VCO Design Challenges and Solutions for mm-wave Applications

Waleed Khalil, The Ohio State University, USA

ABSTRACT:

According to the IEEE Xplore, there have been over 18,000 articles published describing new VCO architectures, circuits and analyses techniques, of which more than 1500 articles have been dedicated to mm-wave VCOs alone. Such a profusion of research, while presenting a clear advancement in the field of mm-wave VCO design and analysis, presents a challenge to designers that are trying to digest the practical limitations and potential trade-offs in the design process. This tutorial attempts to present the fundamental knowledge base for mm-Wave VCOs in silicon technologies. Secondly, the key challenges that the designers face during the process of design and performance optimization will also be enumerated and addressed. In the final part, we will walk through several current and emerging techniques that can be utilized, at circuit architecture and layout levels, toward building robust mm-wave VCOs, while also enhancing their tuning range, phase noise and power efficiency. Overall, the talk is designed to spur analytical thinking on a variety of mm-wave VCO design techniques and challenges, while also offering a new perspective in addressing these challenges.

BIO:

Waleed Khalil leads a multidisciplinary research team in high performance clocking circuits, GHz data converters, digital intensive RF and mm-wave circuits and systems, and more lately in hardware security. He is currently serving as an Associate Professor at the ECE department and the ElectroScience Lab, The Ohio State University. Prior to joining OSU in 2009, he spent 16 years at Intel Corporation where he held various positions in wireless and wireline communication groups. Dr. Khalil is the recipient of OSU’s College of Engineering Lumley Research Award and Fred H. Pumphrey’s Distinguished Teacher Award. His research group has received several paper awards, among them TSMC’s outstanding research award and best paper awards in several conferences. He authored 16 issued and several other pending patents, over 100 journal and conference papers and three books/book chapters. He is a senior member of IEEE and served as an Associate Editor for the Journal of Solid State Circuits (JSSC) and the general chair for the 2020 RFIC Symposium. He is also currently serving as the Editor-in-Chief for the IEEE RFIC Virtual Journal (RFIC-VJ).

 

1:30pm-3:00pm CDT

ES2-3: Efficiency and Linearity Considerations for 5G & mm-wave CMOS Power Amplifiers

Patrick Reynaert, KU Leuven, Belgium

ABSTRACT:

This educational talk will start from the basic limitations in CMOS for mm-wave circuit operation, and gradually look more into large-signal and power-delivery limits of CMOS. Next, the system-level aspects of 5G mm-wave will be briefly discussed, especially their impact on the power amplifier performance. Several PA topologies will be presented and their usefulness in the mm-wave range will be investigated. Finally, several examples of mm-wave PAs, ranging a frequency range from 20 to 100GHz, and using 40nm and 28nm CMOS and 16nm finfet, will be shown and discussed during this presentation.

BIO:

Patrick Reynaert received the Ph.D. in Engineering Science from the Katholieke Universiteit Leuven (KU Leuven), Belgium in 2001 and 2006 respectively. During his Ph.D. degree, his main research focus was on CMOS RF power amplifiers and analog circuit design for mobile and wireless communications. During 2006-2007, he was a post-doctoral researcher at the Department of Electrical Engineering at the University of California at Berkeley. Since October 2007, he is a Professor at KU Leuven, Department of Electrical Engineering (ESAT) and a staff member of the MICAS research group. His main research interests include line-drivers and power amplifiers in CMOS, SOI, GaAs and GaN, mm-wave and THz circuits for communication and sensing and polymer microwave fiber. He is a Senior Member of the IEEE and chair of the IEEE SSCS Benelux Chapter. He has served on the TPC of ISSCC, RFIC, IEDM, ESSCIRC, ICECS and PRIME. He received the 2011 TSMC – Europractice Innovation Award and the 2014 Bell Labs Prize.

 

3:15pm-4:45pm CDT

ES2-4: SOI Technology for 5G and mm-wave Circuits

Andreia Cathelin, STMicroelectronics, France

ABSTRACT:

This talk will first present a short overview of the major analog, RF and mmW technology features of the 28nm fully depleted silicon-on-insulator (FD-SOI) technology. Then we will focus on the benefits of FD-SOI technology for analog/RF and millimeter-wave circuits. Design examples for 5G applications in the low GHz and mmW bands will be illustrated: analog low-pass filters, inverter-based analog amplifiers, several mmW power amplifiers, as well as mmW oscillators and data converters. The fil rouge of all the presentation will come from the FD-SOI specific body biasing features and the special design techniques enabled with it, offering state of the art performance.

BIO:

Andreia Cathelin, an Electrical Engineer with a PhD and HDR from the University of Lille, France, is a Technology R&D Fellow with STMicroelectronics, in Crolles, France. Her focus areas are in the design of advanced RF/mmW/THz and ultra-low-power circuits and systems. She is a key design scientist in the promotion of all advanced CMOS technologies developed in the company and more particularly FD-SOI, doing active promotion through technical and scientific books, international forums, invited talks in high reputation research labs and SOI Consortium events. She is very active in the IEEE community, strongly engaged with SSCS, the Executive Committees of ISSCC and VLSI Symposium and serves as the TPC chair of ESSCIRC2020/21 in Grenoble. Very recently, Andreia has been awarded an Honorary Doctorate from the University of Lund, Sweden in 2020.

 

Educational Session 3: Emerging Applications for Digital Accelerators

9:00am-4:45pm CDT

Session Chairs: Jie Gu, Northwestern University, USA & Gregory Chen, Intel Corporation, USA

 

9:00am-10:30am CDT

ES3-1: Data Analysis for Next-Generation Sequencing – from Basics to Dedicated Accelerators

Chia-Hsiang Yang, National Taiwan University, Taiwan    

ABSTRACT:

DNA sequencing is the process of determining the precise order of nitrogenous bases within a DNA molecule. It is now an indispensable tool for determining the cause of genetic diseases and for developing associated treatments. Next-generation sequencing (NGS) is currently the fastest sequencing technique and can sequence the short fragments in a massively parallel fashion, achieving orders of magnitude higher throughput than the first-generation sequencing technique. Usually, hundreds-of-millions short reads are generated for succeeding data analysis for one whole human genome. The NGS data analysis workflow consists of preprocessing, short-read mapping, haplotype calling, and variant calling. The outputs of variant calling indicate the location and likelihood of each variant (genetic mutation), which can be used for further diagnosis or medical treatment. As the throughput of the NGS sequencing machine grows exponentially, the succeeding data analysis becomes dominant. NGS data analysis could take up to several days to discover all variants of a human genome. The excessive analysis time can be significantly reduced through hardware acceleration. This tutorial gives an overview of NGS data analysis workflow and design examples of dedicated accelerators.

BIO:

Chia-Hsiang Yang received his Ph.D. degree in Electrical Engineering from the University of California, Los Angeles in 2010. He was a professor at the National Chiao Tung University from 2011 to 2015. He is currently a Full Professor at the National Taiwan University. His research group is developing energy-efficient integrated circuits and architectures for AI, biomedical, and communication signal processing. He was a co-recipient of the 2013 ISSCC Distinguished-Technical-Paper Award and Demonstration Session Certification of Recognition. He was a recipient of the Wu Ta-You Memorial Award from the Ministry of Science and Technology (MOST), Taiwan in 2018. He has served on the IEEE Asian Solid-State Circuit Conference (A-SSCC) TPC and ISSCC SRP Committee. He also served as a Guest Editor of the IEEE Journal of Solid-State Circuits (JSSC) and is serving as an Associate Editor of the IEEE Signal Processing Letters (SPL).

 

10:45am-12:15pm CDT

ES3-2: Distributed, Autonomous and Collaborative Multi-Agent Systems

Vinayak Honkote, Intel, India

ABSTRACT:

Multi agent systems have gained increased attention and swift expansion in recent years, primarily fueled by the availability of cost-effective sensors, advancements in compute capabilities and innovations in mechanical form factor design. These systems achieve collective intelligence by ensuring autonomous/decentralized control with the agents coordinating locally to accomplish complex tasks. Multi agent systems are preferred over single agent systems due to scalability, robustness, efficiency and cost considerations. However, advanced robotic systems have, to date, required large investment, intensive computational power and lack the heterogeneity and scalability. Efficient implementation and deployment of these systems have the potential to revolutionize a wide range of complex applications including industrial automation (smart factories), search & rescue, precision agriculture, surveillance, entertainment etc. In this tutorial, we will cover (i) overview and characteristics of multi-agent systems (ii) different design aspects in perception, intelligence, navigation and control capabilities (ii) opportunities and practical challenges in devising and deploying such systems and (iv) example implementations including hardware accelerators for efficient multi agent operation.

BIO:

Vinayak Honkote received Ph.D. degree in Electrical Engineering from Drexel University, Philadelphia, PA, USA, in 2010. His Ph.D. research focused on design and automation of ultra-low power resonant clocking technologies. Vinayak joined Intel in 2011, where he is currently a Senior Research Scientist with the Silicon and Systems Prototyping research group in Intel Labs. At Intel, he has worked on multitude of topics including low-power clocking, voltage regulators, system-on-a-chip prototyping, human computer interaction, vision-based interactive display, energy harvesting systems, and near threshold voltage computing. His current research interests include energy efficient computing, low-power clocking, machine learning, robotics and autonomous systems.

 

1:30pm-3:00pm CDT

ES3-3: Machine Learning Applications in Design Automation

Haoxing (Mark) Ren, NVIDIA, USA

ABSTRACT:

Design automation is facing ever-greater challenges as design complexity increases to unprecedented level and design turn-around time often compressed to capture market opportunities. In the meantime, vibrant developments in the machine learning field provide a new revenue of transformative improvements for design automation. In this talk, we will review recent progress of using ML in design automation domain. These applications include applications of classical machine learning algorithms and deep learning algorithms; supervised learning as well as unsupervised learning and reinforcement learning techniques in various design automation areas such as logic synthesis, physical design and verification. We will also discuss our recent ML research in power analysis, testability, physical design, standard cell design, analog design, and ML accelerator design areas. Looking into the future, will the ML transformation push radical and pervasive changes to design automation? We believe it could. We will propose an idea that would help revolutionize design automation with ML.

BIO:

Haoxing Ren is a principal research scientist at NVIDIA. His current research interests are machine learning applications in design automation and GPU accelerated EDA. Before joining NVIDIA, he spent 15 years at IBM working on physical design and logic synthesis tools and methodology. He received many IBM technical achievement rewards including the IBM Corporate Award for his work on improving microprocessor design productivity. He holds over twenty patents and co-authored 50 papers including several book chapters in physical design and logic synthesis. He has received the best paper awards from ISPD and DAC. He is an IEEE senior member and served as a TPC member for DAC, ICCAD and ASPDAC. He earned a PhD degree in Computer Engineering from University of Texas at Austin, a M.S. degree in Computer Engineering from Rensselaer Polytechnic Institute, and M.S/B.S. degrees in Electrical Engineering from Shanghai Jiao Tong University.

 

3:15pm-4:45pm CDT

ES3-4: Coupled Oscillator based Computing: Using Nature to Solve Difficult Problems

Chris Kim, University of Minnesota, USA

ABSTRACT:

In this talk, I will introduce a computing paradigm that exploits the natural tendency of a network of coupled oscillators to settle to the ground state. Our first-of-its kind test chip with more than 500 coupled oscillators implemented in a standard 65nm technology shows that solutions to NP-hard problems such as max-cut can be found with higher efficiency than traditional digital computation. For the chip demonstration, we mapped max-cut problems to the coupling weights and read out the individual phases using on-chip sampling circuits. Extensive testing shows that coupled oscillators can probabilistically explore the energy landscape to find a good minima point. This has implications on a wide range of intractable problems that can be mapped to a quadratic unconstrained binary cost function.

BIO:

Chris H. Kim is a professor at the University of Minnesota. He is the recipient of the UMN Taylor Award for Distinguished Research, SRC Technical Excellence Award, NSF CAREER Award, and Mcknight Foundation Land-Grant Professorship. His group has expertise in digital, mixed-signal, and memory IC design, with special emphasis on circuit reliability, hardware security, memory circuits, radiation effects, time-based circuits, beyond-CMOS technologies, and machine learning hardware. He is an IEEE fellow.

 

 

Educational Session 4: Low Power Wireless for Biomedical Sensing and IoT

9:00am-4:45pm CDT

Session Chairs: Chris Rudell, University of Washington, USA & Steven Bowers, University of Virginia, USA

 

9:00am-10:30am CDT

ES4-1: Ultra-low-power Frequency Reference, on-chip and Crystal Oscillators

Taekwang Jang, ETH Zürich, Switzerland

ABSTRACT:

Miniaturization and Interactive communication have been the two main topics dominating recent research in the internet-of-things. The high demand for continuous monitoring of environmental and bio-medical information has accelerated sensor technologies as well as circuit innovations. Simultaneously, the advances in communication methods and the widespread use of cellular and local data links enabled the networking of miniaturized sensor systems. In such systems, the reduction of sleep power is critical to make them sustainable with limited battery capacity or harvested energy. It makes the ultra-low-power wake-up timer a critical building block that must be designed with a stringent power budget. At the same time, the precise frequency accuracy is also essential to maintaining synchronization for data communication. This session will present fundamentals and recent innovations in ultra-low-power frequency reference circuits for miniaturized IoT systems. Two commonly adopted architectures, on-chip RC oscillators and crystal oscillators, are introduced and discussed in terms of power consumption, noise, temperature sensitivity, line sensitivity, and calibration methods. Finally, a summary of the state-of-the-art designs and related challenges will be introduced.

BIO:

Taekwang Jang received his B.S. and M.S. in electrical engineering from KAIST, Korea, in 2006 and 2008, respectively. From 2008 to 2013, he worked at Samsung Electronics Company Ltd., Yongin, Korea, focusing on mixed-signal circuit design, including analog and all-digital phase-locked loops for communication systems and mobile processors. In 2017, he received his Ph.D. from the University of Michigan; his dissertation was titled “Circuit and System Designs for Millimeter-Scale IoT and Wireless Neural Recording.” After working as a post-doctoral research fellow at the University of Michigan, he joined the ETH Zürich in 2018 as an assistant professor and is leading the Energy-Efficient Circuits and IoT Systems group. At the same time, he is a member of the Competence Center for Rehabilitation Engineering and Science, and the chair of IEEE solid-state circuits society, Switzerland chapter.

He was a co-recipient of IEEE Transactions on Circuits and Systems 2009 Guillemin-Cauer Best Paper Awards. His research interests include ultra-low power systems, bio-medical circuits, frequency synthesizers, and data converters.

 

10:45am-12:15pm CDT

ES4-2: Millimeter-scale Energy-efficient Wireless Transceivers for Minimally-invasive Implants: the Smaller, the Better

Yao-Hong Liu, IMEC, Netherlands

ABSTRACT:

Healthcare technology was fast developing in the past decade, thanks to the advancement of connected wearable sensors, e.g., smart watches, glucose monitors. However, wearables are primarily limited by their precision, due to an unstable skin contact condition. Implantable sensors, on the other hand, are precise, but are often invasive and have higher risk of complication. With the recent advancement in minimally-invasive (e.g., catheter-based) surgeries, insertable sensors can greatly reduce pain, length of hospital stays and possible long-term complications arising from interconnect penetrating tissue.

 

In this talk, I will provide an introduction to next-generation minimally-invasive implantable/insertable sensors, and how wireless integrated circuits can become a crucial component of the sensing system. This talk will start with an introduction of several propagation modalities adopted for in-body communication, including inductive- and capacitive-(/conductive-) coupling, ultrasound and EM radiation. The second part of the talk will discuss the fundamental trade-offs between energy efficiency and volume of the transceivers. Finally, this talk will end with examples of the state of the art, and a discussion of future circuit design challenges yet to be tackled.

BIO:

Yao-Hong Liu received his Ph.D. degree from National Taiwan University, Taiwan, in 2009. He was with Terax, Via Telecom (now Intel), and Mobile Devices, Taiwan, from 2002 to 2010, working on Bluetooth, WiFi and cellular wireless SoC products. Since 2010, he joined imec, the Netherlands. His current position is Principal Membership of Technical Staff, and he is leading the development of the ultra-low power wireless connectivity. In addition, Dr. Liu received a 5-year personal Consolidator Grant from European Research Council (ERC) in 2020 and is Principal Investigator of “Intranet of Neurons”. He was a recipient of ISSCC 2020 Best System Demonstration Award. His research focuses are energy-efficient RF transceivers and radar for Neural Interface, healthcare and IoT applications. He currently serves as a technical program committee of IEEE ISSCC and RFIC symposium.

 

1:30pm-3:00pm CDT

ES4-3: Deep Sub-Millimeter-Dimension Implants: Challenges and Opportunities

Alyosha Molnar, Cornell University, USA

ABSTRACT:

Wireless biological implants should be made as small as possible, so as to cause as little disruption as possible to surrounding tissue. While implants with dimensions multiple millimeters on a side have existed for some time, only recently has there been real progress toward electronic implants all of whose linear dimensions are well under one millimeter. Two of the biggest challenges with such tiny systems are power delivery and communications. Several different modalities for wireless power transfer and data communications have been proposed, each with its own strengths and weaknesses. But in nearly all cases these systems require tight heterogeneous integration of CMOS electronics with other components, directly impacting both the circuit design and system assembly. Assembly, packaging and encapsulation becomes an increasing challenge as the entire system becomes smaller than a pair of wirebond pads, requiring close co-design of the circuitry itself and subsequent back-end microfabrication techniqes.

BIO:

Alyosha Molnar received his BS from Swarthmore College in 1997, and worked for Conexant Systems from 1998-2001 as an RFIC design engineer, where he jointly developed their first-generation direct-conversion receiver for the GSM cellular standard. Starting graduate school at U.C. Berkeley in 2001, Molnar worked on an early, ultra-low-power radio transceivers for wireless sensor networks, and then joined a retinal neurophysiology group where he worked on dissecting the structure and function of neural circuits in the mammalian retina. He joined the Faculty at Cornell University in 2007, where is an associate professor and works on software-defined radios, neural interface circuits, integrated imaging techniques, and ultra-low power sensing.

 

3:15pm-4:45pm CDT

ES4-4: The Internet-of-Medical Things (IoMT): An Opportunity for Ubiquitous Health Monitoring

Drew Hall, University of California, San Diego, USA

ABSTRACT:

With increases in healthcare costs, a constantly growing population, and a limited supply of physicians, radical changes must be made for the healthcare system to remain sustainable. Consumer electronics are ubiquitous and inexpensive today, whereas most medical devices are costly, and access is primarily limited to hospitals. A compelling solution is to alleviate some of the burden on the healthcare system by equipping individuals with technology to track and monitor their own health. Just as miniaturization of computers, which once filled large rooms, into the microprocessor revolutionized the computer industry, miniaturization of medical devices has the potential to restructure our healthcare system in a similar fashion. This talk will start by introducing biosensors and the challenges in designing power efficient analog front-ends. The second part will describe examples of low power MedRadio transmitters. Case studies will be provided with a focus on the circuit and system-level challenges.

BIO:

Drew A. Hall received the Ph.D. degree in electrical engineering from Stanford University in 2012. From 2011 to 2013, he was a Research Scientist in the Integrated Biosensors Laboratory at Intel Labs. Since 2013, he has been with the University of California at San Diego, where he is currently an Associate Professor in the Department of Electrical and Computer Engineering with an affiliate appointment in the Department of Bioengineering. He leads the multidisciplinary Biosensors and Bioelectronics (BioEE) group which focuses on bioelectronics, biosensors, analog circuit design, medical electronics, and sensor interfaces.

Dr. Hall is an associate editor of TBioCAS, a member of the CICC technical program committee, and a member of the ISSCC technical program committee.