2015 CICC Poster Sessions

Monday Poster Sessions

Poster Session

5:00 pm – 7:00 pm

Siskiyou/Cascade Ballroom

M-1  :  A Linear Transconductance Amplifier with Differential-Mode Bandwidth Extension and Common-Mode Compensation

Derui Kong, Sang Min Lee, Shahin Mehdizad Taleie, Michael Joseph McGowan, Dongwon Seo, Qualcomm Technologies, Inc

A transconductance amplifier with extended bandwidth, which is a critical block in various applications including amplifiers, filters and DACs is presented. The presented technique introduces a differential-mode negative capacitance while introduces the common-mode positive capacitance such that it extends the differential-mode bandwidth and compensates the common-mode stability. The proposed transconductance amplifier has been implemented for a DAC in CMOS 20nm to improve the distortion performance as a negative transconductance circuit, but the proposed technique is applicable to the wide range of circuits with a transconductor.

M-2  :  Low Power Analog Circuit Techniques in the 5th Generation Intel CoreTM Microprocessor (Broadwell)

P. Mosalikanti, N. Kurd, C. Mozak, T. Oshita, Intel Corporation

Fabricated on a 14nm process technology node, the 5th generation CoreTM processors improve energy efficiency over the previous 22nm generation by upto 2.5x. Numerous optimizations in the analog circuits contributed – lower PLL Vmin, 150mV lower clock distribution Vmin, 3x DDR power reduction, 10x lower thermal sensor power and more.

M-3  :  A Compact, High Linearity 40GS/s Track-and-Hold Amplifier in 90nm SiGe Technology

D. Lal, M. Abbasi, D.S. Ricketts, North Carolina State University

We report a 40GS/s Track and Hold Amplifier in 90nm SiGe HBT technology with ENOB>4.9. Up to 19GHz input, SFDR3>68dB, THD3<-31dB and IIP3>+4dBm are measured with 560mW consumed over 0.03mm2 active die area. Linearity is better than existing SiGe and CMOS THAs at 40GS/s and 50GS/s and comparable to 50GS/s InP designs for less than half the power consumption.

M-4  :  A Seizure-detection IC Employing Machine Learning to Overcome Data-conversion and Analog-processing Non-idealities

Jintao Zhang, Liechao Huang, Zhuo Wang, and Naveen Verma, Princeton University

A seizure-detection system is presented wherein the analog frontend performs data conversion and feature extraction with greatly reduced accuracy requirements. A machine-learning algorithm enables retraining of a classification model to compensate feature errors, restoring performance from 443 to 4 false alarms (i.e., at the level of the baseline system).

M-5  :  A 550μm2 CMOS Temperature Sensor Using Self-Discharging P-N Diode with +/-0.1°C (3σ) Calibrated and +/-0.5°C (3σ) Uncalibrated Inaccuracies

G. Chowdhury, A. Hassibi*, Synaptics, *Univeresity of Texas at Austin

A 550µm2 temperature sensor with a p-n diode in a first-order Δ-Σ loop is presented. It offers calibrated inaccuracy of ±0.1⁰C and uncalibrated inaccuracy of ±0.5⁰C over the measured 35⁰C-100⁰C range. This sensor is optimized to implement a distributed thermal monitoring system in large SoCs operating typically above 30⁰C.

M-6  :  A 16-channel, 1-Second Latency Patient-Specific Seizure Onset and Termination Detection Processor with Dual Detector Architecture and Digital Hysteresis

C. Zhang, M. Altaf, J. Yoo, Masdar Institute of Science and Technology

This paper presents an area-power-efficient 16-channel seizure onset and termination detection processor with patient-specific machine learning techniques. The proposed Dual-Detector Architecture (D2A) incorporates two area-efficient classifiers to achieve a high sensitivity and specificity of 95.7% and 98%, respectively. The overall energy efficiency is measured as 1.85μJ/Classification at 16-channel mode.

M-7  :  An Eight Channel Analog-FFT Based 450MS/s Hybrid Filter Bank ADC With Improved SNDR for Multi-Band Signals in 40nm CMOS

Hundo Shin, Rakesh Kumar Palani, Anindya Saha, Fang-Li Yuan*, Dejan Markovic*, Ramesh Harjani, University of Minnesota, *University of California Los Angeles

We present a complete implementation of a hybrid filter bank ADC based on an analog-FFT. The proposed structure enables the signal in each channel of the wide band system to be separately digitized using the full dynamic range of the ADC. The prototype is implemented in 40nm CMOS process.

M-8  :  A 14-bit 0.17mm2 SAR ADC in 0.13µm CMOS for High Precision Nerve Recording

Anh Tuan Nguyen, Jian Xu, Zhi Yang, National University of Singapore

This paper presents a high-resolution, area- and power-efficient SAR ADC for high-precision nerve recording. It features a new “half-split” DAC array with integrated digital calibrations for automatic estimation and calibration of capacitor mismatches. As a result, the ADC precision can be substantially improved given the constraints on area and power.

M-9  :  A 0.04-mm2 0.9-mW 71-dB SNDR Distributed Modular ΔƩ ADC with VCO-based Integrator and Digital DAC Calibration

Y. Yoon, K. Lee, S. Hong, X. Tang, L. Chen, N. Sun, University of Texas at Austin

This paper presents a low-power and small-area VCO-based closed-loop ADC with two highlights. First, the ADC has a distributed modular architecture, which allows the ADC to be easily reconfigured for other resolution specifications. Second, a novel digital DAC mismatch calibration technique is proposed. It ensures high linearity in the presence of large DAC mismatches.

M-10  :  A 16nm Configurable Pass-Gate Bit-Cell Register File for Quantifying the Vmin Advantage of PFET versus NFET Pass-Gate Bit Cells

Jihoon Jeong, Francois Atallah, Hoan Nguyen, Josh Puckett, Keith Bowman, David Hansquine, Qualcomm Technologies, Inc

A 16nm configurable pass-gate bit-cell register file allows a direct comparison of NFET versus PFET pass-gate bit cells for early technology evaluation. The configurable pass gate enables either a transmission-gate (TG), an NFET pass gate, or a PFET pass gate. From silicon test-chip measurement, the register file with PFET pass-gate bit cells achieves a 33% minimum supply voltage (Vmin) reduction in a 16nm FinFET technology and a 40% Vmin reduction in an enhanced 16nm FinFET technology as compared to a register file with NFET pass-gate bit cells. Test-chip measurements highlight the superior benefits of the PFET drive current relative to the NFET drive current at low voltages. The Vmin improvement with a PFET pass-gate bit cell represents a paradigm-shift from traditional CMOS circuit-design practices.

M-11  :  Custom 6-R, 2- or 4-W Multi-Port Register Files in an ASIC SOC with a DVFS Window of 0.5 V, 130 MHz to 0.96 V, 3.2 GHz in a 28-nm HKMG CMOS Technology

Henry Hsieh, Sang H. Dhong, Cheng-Chung Lin, Ming-Zhang Kuo, Kuo-Feng Tseng, Ping-Lin Yang, Kevin Huang, Min-Jer Wang, and Wei Hwang*, TSMC, *National Chiao-Tung University

We describe custom 6R, 2/4W general-purpose register files (GRF) in an ASIC-based SOC, which has roughly a 2~3 X smaller area, 2 X faster speed, and 5 X lower power than a logic-synthesized version. Hardware showed a DVFS window of 0.5 V @circuit, 130 MHz to 0.96 V, 3.2 GHz.

M-12  :  A 14.8µVrms Integrated Noise Output Capacitor-less Low Dropout Regulator with a Switched-RC Bandgap Reference

Raveesh Magod, Naveen Suda, Vadim Ivanov*, Ravi Balasingam*, Bertan Bakkaloglu, Arizona State University, *Texas Instruments

A 14.8μVRMS integrated-noise (10Hz-100kHz) LDO using switched-RC sample-and-hold bandgap and current-mode chopped, any-load capacitor stable error amplifier in 0.25µm CMOS process is presented. It delivers maximum load of 100mA with dropout of 230mV and IQ of 40µA. It achieves PSR of 50dB at 10kHz for programmable output voltage of 1V-3.3V.

M-13  :  A Scalable and Reconfigurable 2.5D Integrated Multicore Processor on Silicon Interposer

Jie Lin, Shikai Zhu, Zhiyi Yu, Dongjun Xu*, Sai Manoj P.D.*, Hao Yu*, Fudan University, *Nanyang Technological University

This paper presents a 2.5D multicore processor, which is flexible to be organized into various multi-chip systems to meet different application requirements. The 2.5D I/O supports 12 way full-duplex communication each by a pair of 8Gbps SerDes, achieving a bandwidth of 24GB/s. The system consumes 1.08W in GF 65nm process.

M-14  :  A 275 Gbps AES Encryption Accelerator Using ROM-based S-Boxes in 65nm

B. Erbagci, N. E. C. Akkaya, C.Teegarden, K. Mai, Carnegie Mellon University

The implementation of the SubBytes (or S-Box) step of the AES algorithm significantly contributes to the area, delay, and power of AES accelerators. Unlike typical logic gate S-Box implementations, we use full-custom 256×8-bit ROMs, which significantly improve performance and efficiency. We implemented a fully-unrolled, pipelined AES-128 encryption accelerator using ROM-based S-Boxes in 65nm bulk CMOS which operates at 2.2GHz and consumes 523mW at 1.0V, 27C. In counter-mode operation (CTR), the throughput is 275.2Gbps, which is 5.2x higher than the highest ever reported in the literature to our knowledge.

M-15  :  Efficiency Improvement Techniques for RF Power Amplifiers in Deep Submicron CMOS

Aritra Banerjee, Rahmi Hezar, Lei Ding, Texas Instruments

Integration of RF power amplifier in CMOS technology can help to reduce total solution cost and achieve small form factor in modern communication systems. This paper reviews recent developments in CMOS based PA architectures including PWM based digital transmitter and outphasing power amplifier and presents a multi-mode outphasing PA.

M-16  :  Wireless Synchronization of mm-wave Arrays in 65nm CMOS

Charles Chen, Aydin Babakhani, Rice University

This paper presents the first wireless synchronization of a mm-wave array, eliminating the need for connecting wires between the array elements. Wireless injection locking is successfully demonstrated and a 3dB bandwidth of 400Hz at a carrier frequency of 50GHz is achieved (frequency stability of 8ppb). The chip includes two on-chip antennas, a power amplifier, a phase-shifter, buffer amplifiers, and a VCO. The chip is fabricated in a 65nm CMOS process and occupies an area of 1.7mm × 3.8mm.

M-17  :  390-640MHz Tunable Oscillator Based on Phase Interpolation with -120dBc/Hz In-Band Noise

Xu Meng, Lianhong Zhou*, Fujiang Lin, Chun-Huat Heng*, University of Science and Technology of China, *National University of Singapore

A tunable oscillator based on phase interpolation has been studied. It utilizes delta sigma modulator to randomly select between the multi-phase outputs of a digitally-controlled injection-locked ring oscillator, thus achieving a low phase noise tunable high frequency reference that can be applied to normal integer-N PLL.

M-18  :  A 0.1-5.0GHz Self-Calibrated SDR Transmitter with -62.6dBc CIM3 in 65nm CMOS

Yun Yin, Yanqiang Gao, Zhihua Wang, Baoyong Chi, Tsinghua University

A 65nm 0.1-5.0GHz self-calibrated SDR transmitter is presented. A complete self-calibration scheme is proposed to alleviate the non-ideal effects, including RF operation frequency deviation, output power control, LO leakage and image suppression. A power mixer RF front-end and a V-I converter with 3rd-order nonlinearity cancellation are adopted to improve the CIM3 performance. A Class-AB/F dual-mode PA is integrated for narrowband applications.

M-19  :  A Field-Programmable Noise-Canceling Wideband Receiver with High-Linearity Hybrid Class-AB-C LNTAs

J. Zhu, P. R. Kinget, Columbia University

A field-programmable noise-canceling wide-band receiver front end with high performance LNTAs is presented. The common-source (CS) and common-gate (CG) LNTAs are split into several cells whose bias point can be individually programmed in class AB or C yielding a highly linear hybrid class-AB-C LNTA. The 40nm LP CMOS receiver prototype can be programmed on the fly to adapt to different RF environments; it was tested in a low noise mode, a high linearity mode and a low power mode. Across these modes, the receiver has maximum gain of 53dB, a minimum NF of 2.2dB, a maximum B1dB of +11dBm, and a maximum OB-IIP3 of +21dBm; the signal path consumes between 15 and 40mA from a 2.5V supply and the LO current varies from 2.2 to 20mA from a 1.1V supply across operating frequencies. The measured LO emission at the antenna port is <-84dBm.

Tuesday Poster Sessions

Poster Session

Siskiyou/Cascade Ballroom

5:00 pm – 7:00 pm

T-1 – A Novel Switched-Capacitor-Filter Based Low-Area and Fast-Locking PLL

M. Amourah, M. Whately, Cypress Semiconductor

A new low-area and fast-locking Phase Locked Loop (PLL) is presented. The proposed PLL employs a new switched capacitor (SC) filter that uses fractional charge integration to implement capacitor multiplication effect. The proposed (SC) filter has a time response similar to the traditional passive filter response while occupying much smaller area. The proposed PLL was built in a 65nm CMOS process with a capacitance multiplication factor of 16 in parallel with a traditional filter for performance comparison. The PLL has an operating frequency range of 200MHz to 2.0GHz. The PLL has period jitter in the order of 0.9ps RMS with acquisition time less than 10µS. Traditional LPF area is 180µm x 340µm while the (SC) LPF area is only 104µm x 84µm cutting LPF area by a factor 7

T-2 – A Low TC, Supply Independent and Process Compensated Current Reference

Chundong Wu, Wang Ling Goh, Chiang Liang Kok, Wanlan Yang and Liter Siek, Nanyang Technological University, Singapore

This paper presents a 10-µA, trim-free, low temperature coefficient, supply independent current reference with process compensation feature. Based on the proposed structure, a 130 ppm/°C temperature coefficient current reference across -40°C to 80°C temperature range is achieved.

T-3 – A 72µW, 2.4GHz, 11.7% Tuning Range, 212dBc/Hz FoM LC-VCO in 65nm CMOS

Joo-Myoung Kim, Jae-Seung Lee*, Suna Kim*, Taeik Kim, Hojin Park, and Sang-Gug Lee*, Samsung Electronics, *KAIST

An ultra-low power and wide tuning range LC-VCO is presented, where the performances are improved by identifying and avoiding the Q-factor degradation factors in the LC-tank. By the positioning analysis and adoption of MIM capacitor arrays along with minimum size varactors, the proposed VCO with a high-Q inductor, implemented in a 65-nm CMOS technology, operates from 2.35GHz to 2.64GHz (11.7% tuning) with phase noise of -132.92 dBc/Hz at 1MHz offset while dissipating only 72µW from a 0.6-V supply. The FoM of the proposed VCO is 212dBc/Hz and the widest tuning range is shown in the high-Q oscillators.

T-4 – All-digital SoC Thermal Sensor using On-chip High Order Temperature Curvature Correction

Mehdi Saligane, Mahmood Khayatzadeh*, Yiqun Zhang, Seokhyeon Jeong, David Blaauw, Dennis Sylvester, University of Michigan, *Oracle

Accurate, compact thermal sensors are desirable in many applications, including on-chip temperature monitoring for processors with dynamic throttling and reliability management. Current sensors are limited in either area, robustness, or accuracy. This work sidesteps strong linearity requirements for reference and PTAT elements in the sensor by performing a higher-order fitting of more relaxed PTAT and CTAT elements using an embedded calculation compute engine. A compact 24 × 10µm sensing element (40nm CMOS) achieves inaccuracy of <1°C across 30 chips with 2-point calibration and a resolution of 0.02°C.

T-5 – A Configurable 5.9 μW Analog Front-End for Biosignal Acquisition

Tan Yang, Junjie Lu*, M. Shahriar Jahan, Kelly Griffin, Jeremy Langford, Jeremy Holleman, University of Tennessee, *Broadcom Corporation

This paper presents a configurable analog front-end (AFE) for the recordings of a variety of biopotential signals. The AFE has a mid-band gain from 45.2-71 dB. The low-pass corner is tunable in the range of 70-400 Hz and 1.2-7 kHz. The AFE achieves high noise-power efficiency.

T-6 – Ultra-Low Power Multi-Channel Data Conversion with a Single SAR ADC for Mobile Sensing Applications

Wenjuan Guo, Youngchun Kim, Ahmed Tewfik, and Nan Sun, The University of Texas at Austin

Based on the recently emerging compressive sensing theory, the paper proposes an ultra-low power multi-channel data conversion system whose architecture is almost as simple as a single SAR ADC. The proposed architecture is capable of simultaneously converting multi-channel sparse signals while running at the Nyquist rate of only one channel.

T-7 – A 10.5-b ENOB 645nW 100kS/s SAR ADC with Statistical Estimation Based Noise Reduction

Long Chen, Xiyuan Tang, Arindam Sanyal, Yeonam Yoon, Jie Cong*, and Nan Sun, University of Texas at Austin, George Washington University

This paper presents a power-efficient SNR enhancement technique for SAR ADCs. By accurately estimating the conversion residue, it can suppress both comparator noise and quantization error. Thus, it allows the use of a noisy low-power comparator and a relatively low resolution DAC to achieve high resolution. The proposed technique has low hardware complexity, requiring no change to the standard ADC operation except for repeating the LSB comparisons. A prototype ADC is designed in 65nm CMOS. Its SNR is improved by 7dB with the proposed technique. Overall, it achieves 10.5-b ENOB while operating at 100kS/s and consuming 645nW from a 0.7V power supply.

T-8 – A 12b ENOB, 2.5MHz-BW, 4.8mW VCO-Based 0-1 MASH ADC with Direct Digital Background Nonlinearity Calibration

K. Ragab, N. Sun, The University of Texas at Austin

A direct digital background calibration technique to correct nonlinearity errors in VCO-based 0-1 MASH SD ADCs is presented. The proposed technique altogether corrects VCO gain error, nonlinearity, and capacitor mismatch of the residue generating DAC. It improves SNDR of the prototype ADC from 60dB to 73.4dB in 2.5MHz signal bandwidth. The ADC consumes 4.8mW from 1.8V supply in 180nm CMOS. The measured convergence time is only 64ms.

T-9 – A 130nm Canary SRAM for SRAM Dynamic Write VMIN Tracking across Voltage, Frequency, and Temperature Variations

A. Banerjee, J. Breiholz, B. H. Calhoun, University of Virginia

This paper shows the first silicon results of a working 512b canary SRAM using bitline and wordline type reverse assists in a 130nm bulk technology. The 512b canary SRAM has distinct canary failure trends across voltage, frequency, and temperature variations to track an 8Kb SRAM’s dynamic write VMIN.

T-10 – A Low Energy SRAM-based Physically Unclonable Function Primitive in 28 nm CMOS

A. Neale, M. Sachdev, University of Waterloo

A 0.6V low energy 64-kb SRAM-based PUF protected with a multi-bit ECC is fabricated in a 28nm LP-CMOS process. Majority voting and data integrity masking is used to reduce the parity-bit overhead by 65% to yield 100% reproducible PUF responses. Measurement results show an average active access energy of 0.045fJ/bit-cycle.

T-11 – A 0.4V~1V 0.2A/mm2 70% Efficient 500MHz Fully Integrated Digitally Controlled 3-Level Buck Voltage Regulator with On-Die High Density MIM Capacitor in 22nm Tri-Gate CMOS

Pavan Kumar, Vaibhav A. Vaidya, Harish Krishnamurthy, Stephen Kim, George E. Matthew, Sheldon Weng, Bharani Thiruvengadam, Wayne Proefrock, Krishnan Ravichandran, Vivek De, Intel Corporation

Circuit techniques to reduce inductor size are attractive to increase power density for On-Die Voltage Regulators. This paper presents a 70~72% efficient, 500MHz digitally controlled 3-level Buck VR on 22nm Tri-Gate CMOS with MIM capacitors. The advantages of the 3-level converter for wide range DVFS over traditional solutions are demonstrated.

T-12 – A Single-Inductor 7+7 Ratio Reconfigurable Resonant Switched-Capacitor DC-DC Converter with 0.1-to-1.5V Output Voltage Range

Loai G. Salem, Patrick P. Mercier, University of California San Diego

This paper demonstrates the first 7-ratio resonant switched capacitor (SC) converter using only a single inductor, in CMOS. A frequency-scaled-gear-train recursive topology is introduced that enables soft-charging of all flying-capacitors through one inductor at any arbitrary binary ratio. The converter achieves 14.4% efficiency improvement over co-fabricated SC in 0.18µm bulk.

T-13 – A 83fps 1080P Resolution 354 mW Silicon Implementation for Computing the Improved Robust Feature in Affine Space

Shouyi Yin, Peng Ouyang, Leibo Liu, Shaojun Wei, Tsinghua University

In comparison with the popular feature algorithms in vision applications, AFFINE-SIFT (ASIFT) achieves the highest robustness in terms of illumination, rotation, and scale in affine space but exhibits high computation complexity. This work proposes three optimization techniques, including reverse based pipelined affine computing, full parallel Gaussian pyramid computing and rotation invariant binary pattern (RIBP) based feature vector computing, to accelerate the computation intensive parts in ASIFT, and design a high efficient pipelined and parallel architecture for the whole ASIFT. Using TSMC 65 nm process, silicon implementation shows that this work achieves the processing speed of 83fps@1080p (1000 feature points per frame on average) with 200 MHz while dissipating 354 mW. It fully supports the real time processing of high resolution images in vision scenes with strong robustness.

T-14 – A 10 mW 60GHz 65nm CMOS DCO with 24% Tuning Range and 40 kHz Frequency Granularity

Ahmed I. Hussein*, Shadi Saberi**, Jeyanandh Paramesh*, *Carnegie Mellon University, *Broadcom Corporation

A wide tuning range 60GHz DCO with fine frequency step is presented. Different tuning techniques are combined to achieve 24% tuning range with a fine frequency resolution of 39 kHz. The phase noise at 1 MHz is -95.1dBc/Hz. The FOM of DCO is -186.4dB which is better than recent DCOs.

T-15 – A Cartesian Feedback-Feedforward Transmitter IC in 130nm CMOS

Sungmin Ock, Hyejeong Song, Ranjit Gharpurey, The University of Texas at Austin

A transmitter architecture based on Cartesian feedback-feedforward is described. A Cartesian feedback loop is used to linearize a transmitter and PA, and the error signal is utilized in a feedforward path to further enhance linearity. A proof-of-concept prototype transmitter IC that is used to linearize an external PA is demonstrated in a 130nm CMOS process. The implementation allows for a 8.7 dB ACLR improvement, compared to an open-loop transmitter, for an output power of 16.6 dBm at 2.4 GHz while employing a 16 QAM LTE signal with 1.4 MHz bandwidth.

T-16 – A 0.6-V, 30-GHz Six-Phase VCO with Superharmonic Coupling in 32-nm SOI CMOS Technology

Dongseok Shin, Sanjay Raman, Kwang-Jin Koh, Virginia Tech

This paper presents a six-phase VCO using a superharmonic coupling technique. Three VCOs are coupled by an inductive network in their tail nodes to generate six-phase outputs. This network also serves as a tail noise filter in each VCO. Therefore, the proposed six-phase VCO can achieve better phase noise performance than typical multiphase topologies. The proposed VCO is implemented in 32nm SOI CMOS process with core area of 0.6×0.5mm2. The VCO can be tuned from 29.24 GHz to 31.56 GHz, a frequency tuning range of 7.6% at 0.6V supply. With each VCO consuming 1.52 mW DC power (4.56 mW total), the measured phase noise is -128 dBc/Hz at 10 MHz offset when VCO output frequency is 31.43 GHz, resulting in -191 dBc/Hz of FOM.

T-17 – A Dual-Tank LC VCO Topology Approaching Towards the Maximum Thermodynamically-Achievable Oscillator FoM

Amir Nikpaik, Abdolreza Nabavi*, Amir Hossein, Masnadi Shirazi, Sudip Shekhar, Shahriar Mirabbasi, University of British Columbia, *Tarbiat Modares University

A dual tank hard-clipping VCO is presented that can approach the maximum thermodynamically achievable oscillator FoM within 3dB. Compared to class-B/C/D/F oscillators, it is capable of reducing both close-in and far-out phase noise (PN). A prototype 4.17-to-4.95GHz VCO achieves -97 and -143 dBc/Hz PN at 30kHz and 3MHz offset, respectively.

T-18 – A DC-to-12.5Gb/s 4.88mW/Gb/s All-rate CDR with a single LC VCO in 90nm CMOS

J. Yoon, S. Kwon, H. Bae, KAIST

The proposed CDR supports reference-less all-rate operation with static fractional divider and asynchronous phase calibration scheme. And the IC features an automatic loop gain control scheme which adjusts the bandwidth of a CDR automatically in the background for optimum BER performance. The power efficiency of the test chip is 4.88mW/Gb/s.

T-19 – A High-Performance, Yet Simple to Design, Digital-Friendly Type I PLL

A. Sharkia, S. Aniruddhan*, S. Shekhar, S. Mirabbasi, University of British Columbia, *Indian Institute of Technology Madras

A 2.2-to-2.8 GHz 6.8 mW Type-I PLL occupies 0.12 mm2 in 0.13-μm CMOS and achieves 490 fs(rms) random jitter, -103.4 dBc/Hz in-band phase noise, -65 dBc reference spur, and 2.5 μs lock-time. Lock range is improved using a saturated-PFD, voltage booster and a digital level shifter, and reference spur is suppressed using a S/H envelope detector.